M48Z35AV
5.0 V or 3.3 V, 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
■
Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■
READ cycle time equals WRITE cycle time
■
Battery low flag (BOK)
■
Automatic power-fail chip deselect and WRITE
protection
■
WRITE protect voltage:
(VPFD = power-fail deselect voltage)
– M48Z35AV: 2.7 V ≤ VPFD ≤ 3.0 V
■
Self-contained battery in the CAPHAT™ DIP
package
■
Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately)
■
Pin and function compatible with JEDEC
standard 32 Kbit x 8 SRAMs
■
SOIC package provides direct connection for a
SNAPHAT® top which contains the battery
■
(s)
ct
28
1
)(s
Pr
e
let
o
SNAPHAT®
battery
bs
O
ct
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od
RoHS compliant
– Lead-free second level interconnect
Pr
e
du
o
PCDIP28
Battery CAPHAT™
28
1
SOH28
let
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bs
O
June 2011
Doc ID 6784 Rev 9
This is information on a product still in production but not recommended for new designs.
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