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1 Spartan-3E FPGA Family Data Sheet DS312 July 19, 2013 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312 (v4.1) July 19, 2013 DS312 (v4.1) July 19, 2013 • Introduction • • Features • Absolute Maximum Ratings • Architectural Overview • Supply Voltage Specifications • Package Marking • Recommended Operating Conditions • Ordering Information • DC Characteristics Module 2: Functional Description • DC Electrical Characteristics Switching Characteristics • I/O Timing DS312 (v4.1) July 19, 2013 • SLICE Timing • Input/Output Blocks (IOBs) • DCM Timing • Overview • Block RAM Timing • SelectIO™ Signal Standards • Multiplier Timing • Configuration and JTAG Timing • Configurable Logic Block (CLB) • Block RAM • Dedicated Multipliers Module 4: Pinout Descriptions • Digital Clock Manager (DCM) DS312 (v4.1) July 19, 2013 • Clock Network • Pin Descriptions • Configuration • Package Overview • Powering Spartan®-3E FPGAs • Pinout Tables • Production Stepping • Footprint Diagrams © Copyright 2005–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 July 19, 2013 Product Specification www.xilinx.com 1
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