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SN74ALVC08PWR
SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 VCC 4B 4A 4Y 3B 3A 3Y 8 RGY PACKAGE (TOP VIEW) 1A DESCRIPTION/ORDERING INFORMATION 1 This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation. The device performs the Boolean function Y = A · B or Y = A + B in positive logic. 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 GND 1B 1Y 2A 2B 2Y VCC • D, DGV, NS, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Max tpd of 2.9 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 3Y • • • • ORDERING INFORMATION PACKAGE (1) TA QFN - RGY ORDERABLE PART NUMBER TOP-SIDE MARKING Tape and reel SN74ALVC08RGYR Tube SN74ALVC08D Tape and reel SN74ALVC08DR SOP - NS Tape and reel SN74ALVC08NSR ALVC08 TSSOP - PW Tape and reel SN74ALVC08PWR VA08 TVSOP - DGV Tape and reel SN74ALVC08DGVR VA08 SOIC - D -40°C to 85°C (1) VA08 ALVC08 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H H L X L X L L LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) A B Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2004, Texas Instruments Incorporated
TI
Texas Instruments Incorporated
U.S.A
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