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SN74ALVC32PW
SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y DESCRIPTION/ORDERING INFORMATION This quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVC32 performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. ORDERING INFORMATION PACKAGE (1) TA (1) SN74ALVC32PW Tape and reel SN74ALVC32PWR Tape and reel TVSOP - DGV SN74ALVC32NSR Tube TSSOP - PW SN74ALVC32DR Tape and reel SOP - NS SN74ALVC32D Tape and reel SOIC - D -40°C to 85°C ORDERABLE PART NUMBER Tube SN74ALVC32DGVR TOP-SIDE MARKING ALVC32 ALVC32 VA32 VA32 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS B OUTPUT Y H X H X H H L L L A LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) A Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2004, Texas Instruments Incorporated
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