SN54/74LS109A
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS109A consists of two high speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise
and fall times of the clock waveform. The JK design allows operation as a D
flip-flop by simply connecting the J and K pins together.
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM
SET (SD)
5(11)
Q
6(10)
CLEAR (CD)
1(15)
CLOCK
4(12)
J SUFFIX
CERAMIC
CASE 620-09
16
1
Q
7(9)
J
2(14)
N SUFFIX
PLASTIC
CASE 648-08
K
3(13)
16
1
D SUFFIX
SOIC
CASE 751B-03
16
1
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
CD
J
K
Q
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
H
q
q
L
ORDERING INFORMATION
Q
L
H
H
L
q
q
H
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
5
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.
2
11
J SD Q
6 14 J SD
Q
4
CP
3
K C Q
D
7 13
VCC = PIN 16
GND = PIN 8
5-1
K C Q
D
15
1
FAST AND LS TTL DATA
10
12 CP
9
