SN54/74LS114A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS114A offers common clock and common clear inputs and
individual J, K, and set inputs. These monolithic dual flip-flops are designed
so that when the clock goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may be allowed to change when
the clock pulse is HIGH and the bistable will perform according to the truth
table as long as minimum set-up times are observed. Input data is transferred
to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
J SUFFIX
CERAMIC
CASE 632-08
14
Q
6(8)
5(9)
CLEAR (CD)
TO
OTHER
FLIP-FLOP
1
Q
4(10)
SET (SD)
K
2(12)
J
3(11)
N SUFFIX
PLASTIC
CASE 646-06
14
1
13
CLOCK (CP)
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
MODE SELECT — TRUTH TABLE
INPUTS
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
OUTPUTS
OPERATING MODE
SD
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
CD
J
K
Q
Q
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
q
L
H
q
L
H
H
q
H
L
q
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4
3
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
SD
Q
SD
Q
9
6 12 K C Q
D
8
5
11
CP
13
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
J
10
2
CP
K CD Q
1
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-1
J
