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TC74AC125F
TC74AC125P/F/FN/FT,126P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC125P,TC74AC125F,TC74AC125FN,TC74AC125FT TC74AC126P,TC74AC126F,TC74AC126FN TC74AC125P/F/FN/FT TC74AC126P/F/FN Quad Bus Buffer Quad Bus Buffer Note: xxxFN (JEDEC SOP) is not available in Japan. TC74AC125P, TC74AC126P The TC74AC125/126 are advanced high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate and double-layer metal wiring C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The TC74AC125 requires the 3-state control input G to be set high to place the output into the high impedance state, whereas the TC74AC126 requires the control input to be set low to place the output into high impedance. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC125F, TC74AC126F Features • High speed: tpd = 4.0 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) • Capability of driving 50 Ω transmission lines. Balanced propagation delays: tpLH ∼ tpHL − • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Pin and function compatible with 74F125/126 TC74AC125FN, TC74AC126FN TC74AC125FT Weight DIP14-P-300-2.54 SOP14-P-300-1.27A SOL14-P-150-1.27 TSSOP14-P-0044-0.65A 1 : 0.96 g (typ.) : 0.18 g (typ.) : 0.12 g (typ.) : 0.06 g (typ.) 2007-10-01
TOSHIBA
株式会社 東芝セミコンダクター＆ストレージ社
日本
半導体部門、DRAM、フラッシュメモリ、プロセッサ、汎用LSI
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