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SN74LS395N
SN74LS395 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate in either a synchronous parallel load or a serial shift-right mode, as determined by the Select input. An asynchronous active LOW Master Reset (MR) input overrides the synchronous operations and clears the register. An active HIGH Output Enable (OE) input controls the 3-state output buffers, but does not interfere with the other operations. The fourth stage also has a conventional output for linking purposes in multi-stage serial operations. 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • Shift Left or Parallel 4-Bit Register • 3-State Outputs • Input Clamp Diodes Limit High-Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 O0 O1 O2 O3 Q3 CP 15 14 13 12 11 10 16 1 OE 9 N SUFFIX PLASTIC CASE 648-08 16 1 1 MR 2 DS 3 P0 4 P1 5 P2 6 P3 7 S 8 GND D SUFFIX SOIC CASE 751B-03 16 1 PIN NAMES LOADING (Note a) HIGH P0 – P3 DS S CP MR OE O0 – O3 Q3 Parallel Inputs Serial Data Input Mode Select Input Clock (Active LOW) Input Master Reset (Active LOW) Input Output Enable (Active HIGH) Input 3-State Register Outputs Register Output LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 5 U.L. ORDERING INFORMATION SN74LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. 7 3 4 5 6 S P0 P1 P2 P3 2 10 9 DS CP OE Q3 MR O0 O1 O2 O3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 11
TI
Texas Instruments Incorporated
U.S.A
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