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SN74AUC1G08DCKR
SN74AUC1G08 SINGLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES374O – SEPTEMBER 2001 – REVISED APRIL 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 2.4 ns at 1.8 V • DBV PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) B 3 4 3 DRL PACKAGE (TOP VIEW) VCC 2 VCC 2 GND 5 1 GND 1 A B A Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 5 3 5 VCC 4 Y 2 GND Y 1 B 4 A Y DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) 3 4 6 GND 2 V R3E 4 GND P B A 1 5 Y 2 A 1 B V W CC I5E NC Y VCC See mechanical drawings for dimensions. NC – No internal connection DESCRIPTION/ORDERING INFORMATION This single 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G08 performs the Boolean function Y + A • B or Y + A ) B in positive logic. ORDERING INFORMATION PACKAGE (1) (2) TA ORDERABLE PART NUMBER TOP-SIDE MARKING (3) NanoFree™ – WCSP (DSBGA) Reel of 3000 0.23-mm Large Bump – YZP (Pb-free) (2) (3) SON – DRY Reel of 5000 SN74AUC1G08DRYR PREVIEW Reel of 3000 SN74AUC1G08DBVR U08_ SOT (SC-70) – DCK (1) _ _ _UE_ SOT (SOT-23) – DBV –40°C to 85°C SN74AUC1G08YZPR Reel of 3000 SN74AUC1G08DCKR UE_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2007, Texas Instruments Incorporated
TI
Texas Instruments Incorporated
U.S.A
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