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TC74AC138F
TC74AC138P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC138P,TC74AC138F,TC74AC138FT 3-to-8 Line Decoder The TC74AC138 is an advanced high speed CMOS 3-to-8 LINE DECODER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y 0 - Y7 ) will go low. When enable input G1 is held low or either G 2 A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G 2 A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC138P TC74AC138F Features • High speed: tpd = 5.9 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines. Balanced propagation delays: tpLH ∼ tpHL − • • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • TC74AC138FT Pin and function compatible with 74F138 Weight DIP16-P-300-2.54A SOP16-P-300-1.27A TSSOP16-P-0044-0.65A 1 : 1.00 g (typ.) : 0.18 g (typ.) : 0.06 g (typ.) 2012-02-29
TOSHIBA
株式会社 東芝セミコンダクター＆ストレージ社
日本
半導体部門、DRAM、フラッシュメモリ、プロセッサ、汎用LSI
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